Applied Computing · Section 2
The Transistor
An imperfect analog switch, and the patient discipline that turns it into perfect digital logic.
Here is the small, slightly scandalous secret underneath every computer ever built: there is no such thing as a digital transistor. The thing on the chip is an analog device — a little voltage-controlled resistor, leaky and lopsided, that conducts better in one direction than the other and never quite reaches the rails you ask it to. "Zero" and "one" are not facts of physics; they are a fiction we impose, by force of engineering, on a smear of continuous voltage. Almost everything that follows — why we build with a thing called CMOS, why every primitive gate insists on flipping its answer upside down, why a whole computer can be made from copies of a single gate, why your laptop fan spins up and your phone throttles when it's hot — falls straight out of the one stubborn fact that the switch is imperfect. Get this idea and a dozen mysteries open at once. So let's start with the imperfection itself.
Chapter One — Theory
1. The Switch That Half-Works
The workhorse of every chip is the MOSFET — a metal–oxide–semiconductor field-effect transistor — and the clean story we tell beginners is that it's a switch. Put a voltage on the gate and a channel opens between the other two terminals, source and drain; current flows. Take the gate voltage away and the channel closes; current stops. Gate high, on. Gate low, off. One and zero. Lovely.
Now here's the part the clean story leaves out, and it's the whole chapter. A transistor that's "on" is not a wire — it's a resistor, with some on-resistance $R_{on}$ that depends on how hard you drive the gate. And it only stays on while the gate sits a threshold voltage $V_t$ above the channel. The instant the gate-to-source voltage $V_{gs}$ falls below $V_t$, the channel pinches shut. That one condition — the gate must stay $V_t$ ahead of the source — is the source of all the trouble.
The NMOS pulls down beautifully and pulls up terribly
Take an NMOS transistor (the kind that turns on when its gate is high). Tie its gate to the high rail $V_{dd}$ and ask it to pull a node down to ground. It does this superbly: as the output falls toward $0$, the source sits near ground, $V_{gs} \approx V_{dd}$ stays huge, the channel stays wide open, and the node slams down to a clean, hard $0$.
Now ask that same NMOS to do the opposite job — to pull a node up toward $V_{dd}$. Watch what happens as the output climbs. The output is the source now, and as it rises, $V_{gs} = V_{dd} - V_{out}$ keeps shrinking. The transistor is throttling itself. By the time the output reaches $V_{dd} - V_t$, we have $V_{gs} = V_t$ exactly, the channel pinches off, and the node stops rising. It never gets to $V_{dd}$. You asked for a $3\,\text{V}$ "one" and you got something near $V_{dd} - V_t$ — and once the body effect is counted (the rising source raises $V_t$ further still), a $3\,\text{V}$ rail through an NMOS can sag to around $1.5\,\text{V}$. That is not a clean one. It's a limp, ambiguous half-voltage that the next gate may or may not believe.
The PMOS (which turns on when its gate is low) is the perfect mirror image. It pulls a node up to a hard, clean $V_{dd}$ — and pulls down only to about $V_t$ above ground, a weak "zero." So we arrive at the rule the rest of the chapter is built on, and it's worth carving in stone:
NMOS pulls down well. PMOS pulls up well. Never ask either to do the other job.
A careful word about electrons and holes
You'll often hear this asymmetry blamed on charge carriers, and it's worth getting straight, because two different true facts get tangled together. An NMOS conducts with electrons; a PMOS conducts with holes (the absence of an electron, which drifts the other way). Electrons are roughly two to three times more mobile than holes, so an NMOS is the intrinsically stronger, faster device — which is exactly why a PMOS has to be built physically wider, often about twice as wide, just to match an NMOS's drive strength. That mobility gap is real, and it costs area on every chip.
But — and this is the careful part — the mobility gap is not why an NMOS can't pull a node high. That is purely the threshold story above: the gate can't stay $V_t$ ahead of a rising source. The carrier type sets how strong each transistor is; the threshold drop sets which direction each one is good at. Keep the two apart and the device never surprises you.
Chapter Two — Theory
2. CMOS — Pair Them Up
So each transistor is good at exactly one job. What's the move? Don't fight it. Use each device only for the thing it's good at — and pair them so that between the two of them, every output is covered. That pairing is CMOS: Complementary Metal-Oxide-Semiconductor. The name is the whole idea. The "MOS" is the device stack — a metal gate over an oxide insulator over a semiconductor channel. The "Complementary" is the discipline: every gate is built from two complementary networks.
The two networks
Every CMOS gate has exactly two halves:
- A pull-up network (PUN) made entirely of PMOS, connecting the output to $V_{dd}$. PMOS pull up cleanly — so this is the only half allowed to deliver a "1."
- A pull-down network (PDN) made entirely of NMOS, connecting the output to ground. NMOS pull down cleanly — so this is the only half allowed to deliver a "0."
And they're wired as logical opposites, so that for any combination of inputs, exactly one network conducts and the other is fully off. When the inputs call for a "1," the pull-up turns on (clean $V_{dd}$) and the pull-down is open. When they call for a "0," the pull-down turns on (clean ground) and the pull-up is open. The output is always yanked hard to a real rail — never floating, never the limp half-voltage of Chapter 1.
The simplest CMOS gate: the inverter
One PMOS on top, one NMOS on the bottom, gates tied together to the input, drains tied together to the output. Trace it:
- Input low. The PMOS (on when its gate is low) turns on and pulls the output up to a clean $V_{dd}$. The NMOS is off. Output = 1.
- Input high. The NMOS (on when its gate is high) turns on and pulls the output down to a clean ground. The PMOS is off. Output = 0.
Low in, high out. High in, low out. Look at what just happened: the simplest possible CMOS gate is an inverter. And it's no accident — it's forced. A PMOS, our only clean pull-up, turns on when its gate is low; an NMOS, our only clean pull-down, turns on when its gate is high. So a low input always reaches for "1" and a high input always reaches for "0." Every single-stage CMOS gate inverts. You cannot build a non-inverting gate out of one CMOS stage, no matter how clever you are. This is why people call CMOS "inverting logic" — you spend your whole life flipping things back over.
The hidden gift: no static current
There's a bonus buried here that decided the entire industry. Because exactly one network conducts at a time, in steady state there is no direct path from $V_{dd}$ to ground. The on-network holds the output at a rail; the off-network is an open circuit. So a CMOS gate sitting still draws essentially no current at all — it burns power only in the brief instant it switches. Older logic families kept a resistor permanently tied to $V_{dd}$ and bled current the whole time the output was low. CMOS's near-zero standby power is the reason it swept the field, and it's the seed of the entire power story in Chapter 7.
Chapter Three — Theory
3. The Natural Gate Inverts
Let's build a real two-input gate and watch the duality fall out. Take two NMOS in series for the pull-down network: the path to ground is complete only when both are on — that is, only when input A and input B are high. So the output gets pulled to "0" only for the input A AND B. For the pull-up, we need the exact opposite: it must conduct whenever the pull-down does not. Two PMOS in parallel do it — either one being on (its gate low) pulls the output high.
Put it together and ask what the output is. It's "0" only when A and B are both high; "1" otherwise. That is NOT(A AND B) — a NAND gate. Four transistors, and notice the structure:
| A | B | PDN (2 series NMOS) | PUN (2 parallel PMOS) | out = A NAND B |
|---|---|---|---|---|
| 0 | 0 | open | conducts → Vdd | 1 |
| 0 | 1 | open | conducts → Vdd | 1 |
| 1 | 0 | open | conducts → Vdd | 1 |
| 1 | 1 | conducts → gnd | open | 0 |
Swap the topologies — NMOS in parallel for the pull-down, PMOS in series for the pull-up — and you get NOR, which is NOT(A OR B). Either layout is four transistors. And here is the thing to notice and never forget: the cheap, natural CMOS gates are NAND and NOR, and both of them invert. Series-in-one-network always pairs with parallel-in-the-other. That pairing is exactly De Morgan's laws — $\overline{A \cdot B} = \overline{A} + \overline{B}$ — etched into the wiring. The PUN is forced to be the dual of the PDN, because that's the only way to guarantee one is open precisely when the other conducts.
Why you can't just build an AND
So you want a plain AND gate — output high when both inputs are high, no inversion. Can you build it directly, cheaply, in one CMOS stage? No. Chapter 2 already closed that door: a single CMOS stage always inverts. The cheapest honest path to AND is to build a NAND and then undo the inversion with an inverter:
That is the hassle the device asymmetry forces on us, in one line. A NAND costs four transistors; an AND costs six — fifty percent more — purely because the universe hands us an inverting switch and makes us pay an inverter's tax to climb back out. The "obvious" gates of a logic textbook (AND, OR) are the expensive ones in silicon; the "weird" inverting gates (NAND, NOR) are the cheap, fundamental ones. Once you internalize that, a lot of how chips are actually built stops looking strange.
Chapter Four — Theory
4. One Gate Is Enough
If AND costs an inverter more than NAND, you might grumble at NAND. Don't. NAND has a superpower that more than pays for the asymmetry, and it's one of the most beautiful facts in all of computing: NAND is functionally complete. Every Boolean function that can exist — every adder, every multiplexer, every processor that will ever be designed — can be built out of nothing but NAND gates. (NOR is complete too, and by the same argument.)
The proof is almost embarrassingly short. To build any logic you only need three operations: NOT, AND, and OR. So show that NAND gives you all three:
| You want | Built from NAND | Why |
|---|---|---|
| NOT A | NAND(A, A) | NAND(A,A) = NOT(A·A) = NOT A |
| A AND B | NOT( NAND(A, B) ) | invert the NAND |
| A OR B | NAND( NOT A, NOT B ) | De Morgan: A+B = NOT(Ā·B̄) |
That's it. With NOT, AND, and OR all expressible in NAND, anything at all is reachable. Tie a NAND's inputs together and it becomes an inverter — so NAND is secretly "NOT and AND fused into one inverting package," and that built-in NOT is exactly the ingredient that makes it universal. (An AND gate alone is not complete: with no way to invert, you can never produce a "0" from all-"1" inputs.)
Why a fab loves this
This isn't a parlor trick — it's an engineering windfall. If a single gate can express everything, then a chip foundry can pour its effort into perfecting, characterizing, and verifying essentially one circuit, and trust that a whole computer assembled from copies of it will behave. Real chips are laid out from a standard-cell library — a catalog of pre-designed gates — and NAND, NOR, and the inverter sit at its heart precisely because they're the cheapest gates and they're universal. The synthesis tool that turns a hardware description into a layout spends much of its life mapping your logic onto seas of these few inverting cells. One imperfect switch, paired with its complement, multiplied a few billion times — that's a processor.
Chapter Five — Theory
5. The Toolkit
Everything from the first four chapters, on one card. First the device, then the gates it builds.
| Transistor | Turns on when gate is… | Carrier | Pulls cleanly toward… | Mangles… |
|---|---|---|---|---|
| NMOS | high | electrons (more mobile → stronger) | ground (clean 0) | Vdd → stalls at Vdd−Vt |
| PMOS | low | holes (less mobile → sized ~2× wider) | Vdd (clean 1) | ground → stalls at Vt |
| Gate | Function | PDN (NMOS) | PUN (PMOS) | Transistors | Inverts? |
|---|---|---|---|---|---|
| INV | NOT A | 1 | 1 | 2 | yes |
| NAND2 | NOT(A·B) | 2 series | 2 parallel | 4 | yes |
| NOR2 | NOT(A+B) | 2 parallel | 2 series | 4 | yes |
| AND2 | A·B | NAND2 + INV | 6 | no | |
| OR2 | A+B | NOR2 + INV | 6 | no | |
| XOR2 | A⊕B | several inverting stages | ~8–12 | — | |
| NANDN | NOT(A·B·…) | N series | N parallel | 2N | yes |
The first five chapters built logic out of the imperfect switch. The next two count the bill: every "on" transistor is a resistor (that costs you time), and every switching transistor dumps charge (that costs you power). Both bills are written in the same currency — and a single dial pays them.
Interactive — Practice
▸ Interactive Lab
Now it's your turn. Everything below is live. There are two benches. The first, The Device & The Gate, lets you see the imperfect switch directly — the clean rails CMOS gives you, the weak "1" an NMOS can't escape, the transistor cost of every gate, and why a series stack is slow. The second, The Cost, turns the dials of real chip design: voltage against power, energy against battery life, cores against the thermal ceiling. Keyboard works too — focus any slider and the arrow keys nudge it; Home and End jump to the extremes.
Switching a transistor dumps charge, and that costs power. These four benches are the dials a chip architect actually turns — and every one of them, in the end, is the same voltage knob.
Chapter Six — The Cost
6. Latency — Series vs Parallel
An "on" transistor is a resistor $R_{on}$, and every wire and gate input it drives is a capacitor $C$. Charging a capacitor through a resistor takes time — the classic $RC$ delay. So the speed of a gate is set by how much resistance stands between the rail and the output, and how much capacitance has to be charged through it. That single sentence explains why series is slow and parallel is fast.
Series: resistances add, and it's worse than you think
Stack $k$ transistors in series — as the pull-down of a $k$-input NAND does — and to pull the output low, charge must drain through all $k$ of them, one after another. The resistances add: the path is about $k \cdot R_{on}$. But it's actually worse, because each junction between the stacked transistors is its own little capacitor that also has to be discharged, and the charge from the top of the stack sees the resistance of everything below it. Add that up — it's the Elmore delay — and the delay grows not linearly but roughly with the square of the stack height:
Four in series isn't 4× a single transistor's delay — it's about 10×. That quadratic is why you almost never see a gate with more than three or four inputs in a real library: a tall stack is a slow stack.
Parallel: one transistor's worth of resistance
Now put those same $k$ transistors in parallel, as the pull-down of a $k$-input NOR does. Any one of them being on completes the path to the rail, and the paths share the load — so the output sees only about one transistor's resistance, $R_{on}$, no matter how many you stack up. The delay stays flat. This is the deep reason a NOR's pull-down (parallel NMOS) is fast while its pull-up (series PMOS) is slow — and why a NAND, with its series NMOS pull-down, has the opposite balance.
The practical upshot: when you need a wide function, you don't build one tall gate, you build a balanced tree of small ones. An 8-input AND becomes a tree of 2-input gates of depth $\log_2 8 = 3$, and the whole thing is far faster than a single 8-high stack would be. Logic depth, not gate count, is what your clock period pays for. Figure 4 lets you watch the series curve bend upward while the parallel one stays pinned flat.
Chapter Seven — The Cost
7. Power, Energy & Heat
Where does a chip's power actually go? Into two buckets, and they behave completely differently. One is paid only when the logic switches; the other is paid every instant the chip is powered, switching or not.
Dynamic power — the cost of changing your mind
Every time a node flips, the gate driving it charges (or discharges) that node's capacitance through the transistor's resistance. Charging a capacitor $C$ to a voltage $V$ stores energy $\tfrac12 C V^2$; discharging it dumps that energy as heat. Do this $f$ times a second across the whole chip and you get dynamic power:
where $\alpha$ is the fraction of nodes actually switching each cycle. Now here's the move that makes voltage the master dial. A higher voltage doesn't just cost more per switch — it also lets each gate switch faster, so you can run the clock higher: $f$ rises roughly in proportion to $V$. Substitute $f \propto V$ and the $V^2$ becomes a $V^3$:
This cubic is why undervolting is such a powerful lever, and it points to an obvious wish: just run at the lowest voltage you can. But the wish has a hard floor. Drop $V$ too close to the threshold $V_t$ and the transistor barely turns on — gates get sluggish (latency blows up, exactly the $RC$ story from Chapter 6, since $R_{on}$ soars as $V \to V_t$) and start behaving unreliably, misreading their own inputs as noise swamps the shrinking signal. So you can't chase the cubic forever; you stop at the lowest voltage that still switches cleanly and meets timing.
When part of the chip isn't needed at all, there's a cleaner saving than slowing it down: cut its power entirely. Power gating inserts a "sleep transistor" that disconnects an idle block from the supply, so it draws essentially nothing — not even the leakage it would bleed if merely idle. We'll see in a moment why that matters so much.
Static power — the cost of merely existing
Remember Chapter 2's gift: a CMOS gate at rest has no path from $V_{dd}$ to ground, so it should draw no current. Should. But a transistor that's "off" is not perfectly off — a tiny leakage current trickles through it anyway (subthreshold conduction through the channel, and tunneling through the ever-thinner gate oxide). Summed over billions of transistors, that trickle becomes static power: watts burned doing absolutely nothing.
Leakage is the villain of modern chips. It rises sharply as transistors shrink and as you lower $V_t$ (the very thing you'd want to do to allow a lower $V_{dd}$) — which is the cruel knot at the center of low-power design: lowering the supply voltage helps dynamic power cubically, but the threshold reduction that enables it makes leakage explode. This is the reason power gating exists. You can't switch leakage off by standing still; the only way to stop a block from leaking is to disconnect it from the supply altogether.
Energy, battery life, and the ceiling called TDP
Power is the rate of using energy; what you actually care about is energy, the area under the power curve over time:
Energy is what your battery stores and what your electricity bill meters. And here's a result worth holding onto: the energy to switch a gate once is $C V^2$ — it doesn't depend on $f$ at all. So to do a fixed amount of work, lower voltage means less energy, period (until leakage during the longer run-time claws some back — which is why total task energy bottoms out at a sweet-spot voltage rather than at the threshold; you saw the U-curve in Figure 7).
The other number that rules a chip's life is its thermal design power (TDP) — the maximum sustained power the package and cooling can shed as heat. Exceed it and the chip cooks. TDP is a hard ceiling, and total power consumption — dynamic plus static, summed over every active block — must stay under it. On a modern many-core chip the sum of all blocks running flat-out would blow past the TDP, so they simply can't all run at once. This is where the two cost chapters collide: power gating keeps total power under the maximum the chip is allowed to draw, dynamic voltage-and-frequency scaling trims the active blocks down to fit, and the silicon left unpowered is the "dark silicon" the industry has lived with since voltage scaling stalled. The dial that pays the time bill (Chapter 6) and the dial that pays the power bill (this chapter) turn out to be the same knob: voltage.
Chapter Eight — Applications
8. Real-World Uses
Six places the imperfect switch and its consequences shaped real machines and real decisions. Notice the same fingerprints in every one: the device asymmetry, the universality of one gate, and the iron arithmetic of power.
Apollo: a Moon computer built from one gate
The problem. In the early 1960s, MIT had to build a guidance computer reliable enough to fly humans to the Moon and back, using parts that could be qualified to never fail. Every distinct component type is a separate reliability risk to characterize, test, and trust.
The move. They leaned on functional completeness. The Apollo Guidance Computer's logic was built almost entirely from a single kind of gate — a three-input NOR (in resistor–transistor logic) — about 5,600 of them. Because NOR is universal, that one cell could express the entire machine: every adder, register, and control path.
The punchline. Qualifying one gate to spaceflight reliability, then trusting copies of it, was a far smaller risk than a zoo of part types. The completeness theorem from Chapter 4 wasn't abstract algebra — it was a mission-assurance strategy that helped put people on the Moon.
Why CMOS won — the power wall of the 1980s
The problem. Early microprocessors used NMOS-only logic, which pulls down with a transistor but pulls up through a permanently-connected load. That load conducts a steady current the entire time an output sits low — the chip burned watts doing nothing, and ran hot.
The move. CMOS. With a complementary pull-up, exactly one network conducts at a time, so there's no standing path from $V_{dd}$ to ground (Chapter 2). A CMOS chip at rest draws almost nothing — only leakage.
The punchline. That near-zero standby power is why every processor on Earth is CMOS today. The device asymmetry forced the complementary structure, and the complementary structure handed back, almost as a gift, the lowest idle power any logic family had ever seen.
The weak-1 trap: pass-transistor logic that "works in sim"
The problem. To save area, a designer builds a multiplexer or an XOR out of bare NMOS "pass transistors." In simulation it's perfect. On silicon it's flaky: the high level sags to about $V_{dd}-V_t$, and the next stage either misreads it or — worse — never fully turns off, bleeding "crowbar" current and overheating.
The move. Restore the level. Either pair each NMOS with a PMOS to form a full transmission gate (now one device always pulls the level cleanly), or follow the pass logic with a CMOS buffer that re-establishes a real rail.
The punchline. This is Chapter 1's $1.5\,\text{V}$ "weak 1" biting a real engineer. The device asymmetry isn't a textbook curiosity — it's a bug waiting for anyone who forgets that an NMOS can't pull high.
DVFS: the reason your phone sips and sprints
The problem. A phone must feel instant under load yet barely sip power when idle, all from a tiny battery and no fan. Running flat-out always would melt it; running slow always would make it feel dead.
The move. Dynamic voltage-and-frequency scaling. The SoC continuously adjusts both voltage and clock together — dropping both when idle, snapping both up for a burst. Because dynamic power is cubic in voltage (Chapter 7), the idle state costs almost nothing.
The punchline. The cubic law makes the saving enormous: trimming the operating point even modestly cuts power by a large fraction. Pair that with "race to idle" — sprint, finish, then power-gate to sleep — and a phone can feel fast and still last all day. Every modern SoC does this thousands of times a second.
Power gating and the rise of dark silicon
The problem. As transistors shrank, leakage grew until a chip could no longer afford to power all of its silicon at full speed at once without exceeding its TDP. The package simply can't shed that much heat.
The move. Carve the chip into dozens of independently power-gated domains, each with sleep transistors that cut its supply when it's not in use — so an idle block draws essentially zero, not even leakage. Schedule work so the active set always fits under the thermal ceiling.
The punchline. The unpowered remainder is "dark silicon," and there's more of it every generation. A modern SoC is less a single engine than a fleet of specialized blocks, most of them asleep at any instant — power gating is what keeps total draw under the maximum the chip is allowed (Chapter 7).
The end of the free lunch: why clocks stopped at ~4 GHz
The problem. For decades, each transistor shrink let engineers lower the voltage too (Dennard scaling), so power density stayed roughly constant even as clocks climbed. Then, around 2005, voltage scaling stalled — you couldn't keep lowering $V_t$ without leakage exploding, and you couldn't lower $V_{dd}$ without it.
The move. With the cubic power law no longer being tamed by falling voltage, pushing frequency higher meant pushing power through the roof. So the industry stopped chasing GHz and pivoted: more cores instead of faster ones, plus the whole toolkit of DVFS and power gating to manage the heat.
The punchline. This is why your CPU still clocks around 3–5 GHz, the same as fifteen years ago, but has many cores. The transistor kept shrinking; the voltage stopped falling — and that single broken assumption rerouted the entire trajectory of computing.
Chapter Nine — Practice
9. Sharpen Your Instinct
You've seen the switch misbehave and the dials turn. Here's where you find out whether it's yours. Each of these is a spot a real engineer walks into, and not one of them says "threshold drop" or "Elmore delay" or whispers which idea to reach for. So that's the job: see the imperfect switch showing through the symptom, and name what's really going on. Keep the lab open in another tab to check yourself.
A student wires a single NMOS transistor as a "high-side switch" to drive a $3.3\,\text{V}$ logic input. The gate is tied to $3.3\,\text{V}$, the drain to $3.3\,\text{V}$, and the source goes to the load. They measure about $1.7\,\text{V}$ at the output, and the downstream gate behaves erratically.
(a) Why isn't the output $3.3\,\text{V}$? (b) Give two fixes, and say what each one changes about the device doing the pulling.
You need a 3-input AND in a standard-cell flow. A teammate says "an AND is the cheapest logic there is — just drop one in." You suspect it's not the cheapest.
(a) What's the minimum-transistor way to build a 3-input AND in CMOS, and how many transistors is it? (b) Why can't you build it more cheaply with a single direct gate?
A foundry tells you that, for yield reasons, it will guarantee only one logic cell type at the aggressive node you want. Your design needs a full ALU — adders, multiplexers, the works.
(a) Can you still build the ALU? (b) Which single cell do you ask for, and how would you make a NOT, an AND, and an OR out of it?
You must implement an 8-input function on a tight clock. One engineer proposes a single 8-input gate (one tall transistor stack); another proposes a balanced tree of 2-input gates.
(a) Which is faster, and by roughly how much? (b) What physical quantity makes the tall stack slow?
A phone renders a game smoothly but the battery lasts only two hours. A profiler shows that capping the GPU clock to 85% of its peak — which also lets the voltage drop proportionally — barely hurts the frame rate but noticeably extends battery life.
(a) By roughly what fraction does capping to 85% cut the GPU's dynamic power? (b) Why is the saving so much larger than the 15% clock cut?
A 16-core server chip is rated at $200\,\text{W}$ TDP, but if every core ran flat-out simultaneously the chip would draw about $320\,\text{W}$.
(a) How does it run at all without destroying itself? (b) What sets the number of cores that can boost together at any moment?
Solutions
Problem 1 — The weak high. (a) As the source (the output) rises, the gate-to-source voltage $V_{gs} = 3.3 - V_{out}$ shrinks; once $V_{out}$ reaches $3.3 - V_t$ the NMOS pinches off and stops conducting. The body effect raises $V_t$ further as the source climbs, dragging the final level down to about $1.7\,\text{V}$ — a weak "1," not a clean rail. (b) Either (i) use a PMOS as the high-side switch — a PMOS pulls up to a clean $V_{dd}$ — or (ii) keep the NMOS but follow it with a CMOS buffer / transmission gate that restores a full rail. The first swaps in the device that's good at this job; the second adds a clean pull-up to finish the job the NMOS can't.
What breaks this? The assumption that "on" means "connects to the rail." An NMOS connects to a rail $V_t$ short of where it's trying to go, because the gate can't stay ahead of a rising source. That's the entire device asymmetry of Chapter 1, in a single botched circuit.
Problem 2 — The inverter's tax. (a) Build a 3-input NAND — three NMOS in series, three PMOS in parallel, $2N = 6$ transistors — then an inverter (2 transistors) to flip its output. Total 8 transistors. (b) Because a single CMOS stage always inverts (Chapter 2): the only clean pull-up, the PMOS, turns on for a low input. There is no single-stage non-inverting gate, so AND must be NAND-then-invert. The AND is strictly more expensive than the NAND.
What breaks this? The intuition that AND is "fundamental" and cheap. In silicon it's the opposite — NAND and NOR are fundamental and cheap; AND and OR are derived and each carry an inverter's tax. The teammate had the cost hierarchy upside down.
Problem 3 — One cell. (a) Yes. (b) Ask for a NAND (a NOR works equally well — both are functionally complete). Constructions: NOT A = NAND(A, A); A AND B = NOT(NAND(A,B)) = NAND( NAND(A,B), NAND(A,B) ); A OR B = NAND(NOT A, NOT B), since by De Morgan $A+B = \overline{\bar A \cdot \bar B}$. With NOT, AND, and OR in hand, the full ALU follows.
What breaks this? Nothing — that's the point. Completeness is exactly the guarantee that one gate is never a limitation. The only thing that would break it is asking for a gate that can't invert (a bare AND or OR): with no way to make a "0" from all "1"s, you'd be stuck forever.
Problem 4 — Tree beats stack. (a) The tree is much faster. A single 8-input gate is an 8-high series stack whose delay scales like $k^2$ — roughly $\tfrac12 \cdot 8^2 \approx 32$ in normalized units. A balanced tree of 2-input gates has depth $\log_2 8 = 3$ small, fast stages. (b) The series stack's resistance (and the internal-node capacitance it must charge through that resistance) piles up quadratically — the Elmore delay. Resistance × capacitance is time, and a tall stack maximizes both.
What breaks this? The assumption that "fewer gates = faster." What the clock pays for is logic depth (resistance in series), not gate count. A tall single gate has the least area and the worst delay; the tree trades a little area for a lot of speed.
Problem 5 — The cubic. (a) Dynamic power is $P = \alpha C V^2 f$, and capping the clock to $0.85f$ lets the voltage fall to about $0.85V$ as well, so $P \to (0.85)^2 \cdot 0.85 = 0.85^3 \approx 0.61$ of peak — a cut of about 39%. (b) Because frequency and voltage move together: the 15% clock cut also buys a 15% voltage cut, and power depends on the cube of voltage. Three factors of $0.85$ multiply, not one. (The energy to render a fixed frame falls like $V^2 \approx 0.72$ — also a clear win.)
What breaks this? The linear instinct — "15% slower, 15% less power." The $V^3$ law makes small voltage changes huge. But the cube isn't free forever: push voltage too low and the GPU can't hit the frame rate at all ($R_{on}$ soars near $V_t$), so there's a floor.
Problem 6 — Under the ceiling. (a) It never lights all 16 cores at full power at once. The $200\,\text{W}$ TDP is a hard thermal ceiling; the chip uses power gating to keep idle cores at ≈ 0 W and DVFS to trim the active ones, so total draw stays under $200\,\text{W}$. (b) The active-power budget: with each core at, say, $20\,\text{W}$, only about $200/20 = 10$ can run flat-out together; boosting a few cores higher means powering fewer of them. The silicon that stays dark is "dark silicon."
What breaks this? The assumption that a chip can use all of itself at once. Since voltage scaling stalled, it can't — the heat budget forbids it. TDP, not transistor count, is the real limit, and power management is the art of spending it wisely (Chapter 7).
Chapter Ten — Close
10. When the Model Breaks
The whole digital edifice rests on a few quiet assumptions about the switch. Each one is a useful lie, and the skill that separates an engineer from a button-pusher is knowing exactly where each lie tears. State them first: a transistor is a perfect switch; "off" means no current; "1" is reliably 1; and lower voltage is always better. Now break them one at a time.
Assume an "on" transistor is a wire (zero resistance) and an "off" one is a perfect open. Push it: both are false, and each falsehood is a whole chapter. Finite on-resistance means $RC$ delay — the source of all latency (Chapter 6). Finite off-resistance means leakage — the source of all static power (Chapter 7). The "perfect switch" abstraction is precisely the thing that hides both your time bill and your power bill.
Assume a transistor you've switched off carries no current. Push it: subthreshold leakage flows anyway, and it grows exponentially as you lower the threshold $V_t$. Here's the danger — this failure is silent. The chip computes every answer correctly; nothing crashes, no test fails. It just quietly runs hotter and drains the battery faster than your model predicted. A bug that returns the right answer while wasting energy is the hardest kind to even notice — which is exactly why leakage blindsided the industry and ended Dennard scaling.
The cubic law says power $\propto V^3$, so assume you should drive $V$ as low as possible. Push it to the limit: as $V \to V_t$, the gate's drive current collapses and $R_{on} \to \infty$, so the delay $\to \infty$ — the model is screaming an absurd answer (an infinitely slow gate) to tell you that you've broken the on-condition. Just above that, gates switch but noise margins vanish and logic becomes unreliable; and leakage, integrated over the now-glacial run-time, can make total energy climb again. "Lower is better" is true only down to a floor, and the floor is set by the threshold the whole device rests on.
Assume the levels are crisp: a high node is a clean logic 1. Push it: the digital abstraction is painted on top of continuous analog voltage with only finite noise margins. A weak "1" from a pass transistor ($V_{dd}-V_t$, Chapter 1), supply droop, crosstalk, or a setup-time violation can all push a node into the forbidden zone — and when a flip-flop samples a value mid-transition it can go metastable, hovering between 0 and 1 for an unbounded time. "Digital" is a discipline imposed on analog reality, not a property of it, and it holds only while you respect the margins.
We used $f \propto V$ to turn $CV^2f$ into the clean $V^3$ law. Push it: at high voltage the relationship saturates — carrier velocity saturates, wire delay (not transistor delay) starts to dominate, and thermal throttling caps the clock regardless. So past a point you pay the full $V^3$ in power for only sub-linear gains in frequency: the worst possible trade. This is the upper mirror of Probe 3's floor, and together they pin the usable voltage into a narrow window.
| Ask… | If the answer is "no"… |
|---|---|
| Is every node driven by a clean pull (CMOS), not a bare pass transistor? | You may have weak "1"s near $V_{dd}-V_t$ — restore the level. |
| Did I budget leakage, not just switching power? | Your power estimate is silently low and the chip runs hot. |
| Is my voltage safely above the threshold, with noise margin to spare? | Gates get slow and unreliable; expect metastability and errors. |
| Are my gates shallow (trees), not deep (tall stacks)? | The $k^2$ Elmore delay will blow your clock period. |
| Does the active power fit under TDP at all times? | You must power-gate or throttle — you can't light all the silicon. |
Chapter Eleven — Close
11. The One Pattern to Remember
Pull off the mask, and the whole chapter is one idea wearing five costumes.
A transistor is a one-directional analog switch — an NMOS pulls down cleanly, a PMOS pulls up cleanly, and neither does the other job. CMOS is simply the discipline of always pairing the puller you need with its complement. That discipline forces every gate to invert, which makes the inverting gates (NAND, NOR) the cheap and natural ones — and a single inverting gate turns out to be universal. Everything the switch costs you is the analog device refusing to be perfectly digital: its on-resistance costs time ($RC$ delay, worse in series), and its switching and leakage cost power ($CV^2f \to V^3$, plus a leakage floor).
And if you keep just one working habit from all of this, keep the dial. There is one knob — voltage — and it sets your speed, your power, and your reliability all at once: raise it and gates switch faster but power climbs as the cube; lower it and you save enormously until, near the threshold, the switch stops switching. Speed, power, correctness — three faces of a single continuous quantity that we spend the entire discipline of digital design pretending is just a 0 or a 1. The miracle isn't that the transistor is a perfect switch. It's that we built perfect logic out of one that isn't.